Subthreshold Transistors and MCUs

Summary: When Vgs < Vth the world changes.

I would never buy an iWatch. The silly thing must be removed and recharged more or less daily. My myopia makes using a bedside clock impossible, so I need a watch-on-wrist during the night to monitor my insomnia. A cheap Timex runs for years on a single primary cell. The iWatch has a power-hungry SoC, rather than the Timex's minimal bit of logic.

Cheap digital watches use FETs operating in the subthreshold region. For decades we digital folk have ignored this operating region, with good reason. FETs are hard to characterize there. But now subthreshold has invaded the embedded space thanks to Ambiq's (http://ambiqmicro.com/) new Apollo MCU.

The best part of embedded engineering is that one is always learning new things. New ways to design software. New circuit ideas. And now we've got to learn about operating FETs in a region we always tried to avoid.

Actually, that's not completely true. The vendors designing ICs whose transistors operate in the subthreshold region need to be experts at this. We design engineers are presented with an API (the pins on the chip) that work in the usual way. But this technology is so cool who wouldn't want to learn about it?

We think of FETs operating in one of three regions: the first is at cutoff, when no current flows. Then there's the ohmic and saturation modes where the FET is on. But the cutoff, AKA subthreshold, region is actually more interesting than the device simply being "off."

Vth is the threshold voltage; it's the voltage needed to turn a FET on. But when the gate-source voltage (VGS) is less than Vth some electrons do enter the channel, so there is some current flow from the source to the drain. Simplifying things a lot, in the subthreshold region drain current is:

I_D~e^(?qV?_GS/nkT)

Where q is charge, n is a constant, k is Boltzmann's constant, and T is temperature. Obviously, drain current is highly non-linear with the gate-source voltage. And interestingly, this mirrors the Shockley diode equation.

Vth depends on a lot of factors, but is typically around half a volt. This means subthreshold operation is in the couple of tenths of a volt range. That's a scary-low operating level for those of us working in the couple of volts range. But worse, as the equation shows, the drain current is also highly dependent on the FET's temperature. That's a good reason for avoiding operation in this region. But a circuit running there can offer extremely low active power consumption - as much as an order of magnitude lower than in the ohmic region.

34 uA/MHz is something like a tenth of what the ultra-low-power MSP430F11 (using their typical numbers) needs. The latter is only a 16 bitter - and costs roughly the same amount as Ambiq's part.

Ultra-low power design is all about sleeping as much as possible. Wake up, get as much work done as fast as possible, and then go back to sleep. With the M4F you can do an awful lot of work in a very short time, and even during that time the MCU's current needs are tiny compared to alternative processors. At 143 nA (typical) the Apollo's sleep current is similar to other ultra-low-power MCUs. (As I show here - https://www.ganssle.com/reports/ultra-low-power-design.html - there's little difference in battery life between an MCU that needs 0 nA and even 1000 nA while asleep).

Ambiq is somewhat guarded about their technology, but apparently uses calibration structures, on-chip temperature monitors with compensation, and other mysteries shrouded in NDAs.

Not all of the MCU runs in the subthreshold region. Some of the circuits that consume little power or that rarely do anything are designed in the conventional manner. There are about five different power domains to achieve the lowest practical current consumption. The parts are built on standard 90 nm TSMC CMOS lines.

The maximum clock rate is 24 MHz, quite slow by Cortex standards, but the Apollo is targeted at low-power applications where fast clock rates can be a liability (many competing products have much slower max clock rates). It sports half a meg of flash and 64KB of RAM, plus a memory protection unit. Why the MPU? I have no idea. MPUs shine for bigger applications where multiple tasks must be insulated from each other. It's almost as if their FETs use so little current they just tossed everything on-board.

A 10 bit ADC has 13 channels, and can operate independently of the CPU. A window comparator will initiate an interrupt if a particular conversion is inside or outside of some programmed limits. Thus, the CPU can be sleeping while the ADC is monitoring the world.

Different packages are available, including a 2.49 x 2.90 mm 41-pin CSP with 27 GPIO.

Is it a real part? You betcha. I have an eval board in my lab. More details will follow when I have a chance to play with it.

Ultra-low power design is tricky, and too many vendors spout too much nonsense about it. I have written a lot (https://www.ganssle.com/reports/ultra-low-power-design.html) about these issues, and continue to take vendors to task for some outlandish claims.

If you're entranced by electronics, it's time to dust off the textbooks and bone up on FETs operating below Vth. The industry is changing.

Yet again.

Published December 9, 2015